SAR ADC#

Image from White Flye - Own work, CC BY-SA 2.5, Link

Overview#

6 bit CMOS successive-approximation Analog to Digital Convertor (gpdk045) targeting 1V input swing at 100MS/s, employing a custom capacitive DAC and custom dynamic comparator, designed and simulated with Cadence Virtuoso and ADE Assembler (Loop Stability Analysis, AC/DC/Transient Analysis).

Highlights#

• Analog Fundamentals, Analog Simulation (Noise Analysis, Loop Stability Analysis, AC/DC/Transient Analysis, Monte-Carlo, etc.)
• Digital Circuit Design and Device Fundamentals
• 45 nm GPDK CMOS IC Design, EDA Tools (Cadence Virtuoso/Spectre/ADE Assembler, LTspice)
• Power Distribution, Layout and Physical Design Fundamentals

Details#

More Coming Soon!

Logbook#

Nov 15, 2025

• Goals
  • Make a simple inverting amplifier
  • Do simple simulation to see if it works
• Notes
  • Workflow
    • make a new schematic with library manager
    • Design component
    • Create schematic from cellview
    • Make testbench schematic
    • Simulate with maestro
  • Use gpdk045 for transistors
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  • 
  • 
• Next steps
  • Understand how a comparator works (https://arxiv.org/pdf/2209.07259)
    • 
  • Make a comparator to use in the sar adc

Nov 17, 2025

• Goals
  • Make the comparator
• Notes
  • https://arxiv.org/pdf/2209.07259
  • Strong arm latch comparator
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  • 
  • Use HI = 1.1 V
  • 100 MHz CLK
    • Add a delay to the CLK to let it reset first
    • 80% duty cycle
  • Vsource:
    • 
  • CLK:
    • 
  • Vin1=0.5 V, Vin2:
    • 
  • Vout-:
    • 
  • Vout+:
    • 
• Next steps
  • Make sample and hold amplifier
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  • 
  • 

Nov 18, 2025

• Goals
  • Finish Sample and hold amplifier
• https://en.wikipedia.org/wiki/Sample_and_hold
• https://en.wikipedia.org/wiki/Transmission_gate
  • 
  • 
  • 
    • 10 MHz CLK
    • 0 to 1.1 V sweep for Vin
  • 
• https://en.wikipedia.org/wiki/Buffer_amplifier#Impedance_transformation_using_the_MOSFET_voltage_follower
• https://en.wikipedia.org/wiki/Common_drain
  • How to make rail to rail source follower…
• Wait actually the comparator doesnt work at low voltages…
• It’s so bad below like 0.3 or 0.4 V
• Next steps
  • Maybe fix comparator if possible
  • Or just move onto CDAC or the SAR logic

Nov 29, 2025

• Goals
  • Flip the comparator (old one doesnt work at low voltages, flipping everything should fix this)
  • Make the CDAC
  • Work on SAR logic?
    • (ask UBC IT if digital sim is still broken)
• 
• 
• 10 mV resolution around 0
• Negative works as well
• 
• -0.5 V to +0.5 V works as well which should be max input range
• CDAC
• https://electronics.stackexchange.com/questions/460100/capacitor-dac-charge-redistribution
• 
• https://www.analog.com/media/en/training-seminars/tutorials/MT-021.pdf
• Switch unit
  • TG Ain when TRACK
  • TG Bit input of Vref or 0 when ~TRACK
• Digital sim still has error…
  • mb UBC IT can fix? idk…